ASIC & FPGA Design Studio
iOS Universel / Education
A professional ASIC and FPGA workbench. On your iPhone and iPad.
This app is built for hardware engineers, RTL designers, and FPGA developers who want a serious tool — not a quiz app. Every feature is oriented around doing real work: writing HDL, running simulations, looking up syntax, and solving timing problems.
EDITOR & WAVEFORM SIMULATOR
Write Verilog or VHDL in a full syntax-highlighted editor and run a behavioral simulation on-device. Inspect signal waveforms cycle by cycle. A signal analysis panel shows each port's final state with HIGH/LOW indicators. No Vivado, no ModelSim, no laptop required.
ENGINEERING TOOLBOX
Four calculators built into the app:
— Clock & Timing: enter your target frequency and get clock period, combinational path budget, setup slack, and ready-to-paste create_clock constraints for Xilinx Vivado and Intel Quartus.
— Bit Width Advisor: enter a maximum value or state count and get the minimum bit width, Verilog wire/reg declaration, and VHDL signed/unsigned type.
— Pipeline Depth Estimator: enter target frequency and logic path delay to calculate how many pipeline stages are needed to close timing.
— Skew & Jitter Budget: model your clock network with setup time, hold time, jitter, and a configurable design margin to calculate maximum allowable clock skew and routing health.
DESIGN PATTERN LIBRARY
Organized by engineering domain — combinational logic, sequential design, FSMs, memory interfaces, FPGA primitives, ASIC flow, verification, and timing constraints. Each pattern includes annotated HDL templates you can open directly in the simulator with one tap.
HDL REFERENCE
Searchable quick reference for Verilog, VHDL, and SystemVerilog — data types, operators, language constructs, FPGA concepts, ASIC concepts, and a glossary. Filter by category or language. Tap any entry for syntax, example, and explanation.
WHO USES THIS
FPGA engineers working with Xilinx, Intel/Altera, Lattice, or Microchip boards. ASIC RTL designers who want a portable reference. CS and EE students in digital design or computer architecture courses. Anyone who writes HDL and wants their tools with them.
Quoi de neuf dans la dernière version ?
This is a major update that transforms the app into a professional HDL engineering workbench.
New: Engineering Toolbox
Four on-device calculators built for working hardware designers:
Clock & Timing — clock period, setup slack, and ready-to-paste Vivado/Quartus constraints
Bit Width Advisor — minimum bits for any value or state count, with Verilog and VHDL type output
Pipeline Depth Estimator — pipeline stages needed to close timing at your target frequency
Skew & Jitter Budget — maximum allowable clock skew with configurable design margin
Redesigned Experience
New Workbench home with design activity dashboard and quick-access to all tools
Design Pattern Library replaces the old curriculum — organized by engineering domain with HDL templates you can open directly in the simulator
Waveform Simulator now shows a full signal analysis panel below the waveform with per-signal HIGH/LOW final states and a timing diagram reading guide
HDL Editor landing page explains the simulator workflow when the tab is first opened
Visual
Dark navy-purple background applied consistently across Patterns, Reference, and Workbench tabs
Frosted glass row cards throughout list views
